Конфигурационный файл драйвера devg-imx6x.so
/etc/system/config/imx6x.conf
# devg-imx6x.so parameters (see i.MX6DQRM Reference Manual for details)## Each GF display is configured by one line of the input file. When a value is set, it becomes the default value for the following lines.# The defaults are: xres=800,yres=600,refresh=60,hspclk=0,pixclk=40000000,vsw=4,vss=19,vew=5,hsw=128,hss=88,hew=40,vpol=0,epol=1,dpol=0,# cpol=0,hpol=0,yuv=1,layers=2,ofmt=24,up=0,down=15,ldbmap=0,ldbmode=0,ldbwidth=0,di=0. There are 1 or 2 GF displays (not to be confused# with iMX Display Interfaces). The first GF display has support for two layers, resizing, and YUV on one of the layers, and is mandatory.# It can be routed to either DI0 or DI1. The second GF display has only one layer, and can be routed to the other DI, or disabled.## These options may be specified for each display interface:# These settings may be specified on any line, but all instances must have the same value:# board Board type for GPIO settings:# 0 i.MX51 EVK# 1 i.MX53 EVK# 2 i.MX53 SABRE-AI# 3 i.MX6x (default, see "chip" option)# chip Chip type for i.MX register addresses:# 51 i.MX51# 53 i.MX53# 60 i.MX6 Solo (unsupported)# 61 i.MX6 Dual# 63 i.MX6 Quad (default for i.MX6x boards)# 0 guess from 'board' parameter (default)# Display settings:# re-init Disable IPU before starting# 0 initial IPU disable sequence does not needed# 1 disable IPU initially# ipu Display controller index (i.MX6x only):# 0 IPU1 (default)# 1 IPU2# di Display interface index:# 0 DI0 (default)# 1 DI1# type Display type:# 0 DVI (default)# 1 VGA# 2 LVDS (affects GPIO settings to enable board-specific hardware)# ofmt Display output pixel format:# 16 RGB565# 18 RGB666# 24 RGB888 (default)# rotation Display data rotation (i.MX6x only):# 0 0 degrees rotation (default)# 180 180 degrees rotation# extclk External clock frequency, in Hz:# 0 use internal clock (default)# x external clock frequency, in Hz# extvsync Vsync source:# 0 internal (default)# 1 external# hspclk HSP clock frequency, in Hz (default: 133 Mhz (i.MX51) / 200 MHz (i.MX53) / 264 MHz (i.MX6x))# yuv YUV layer index (DI1 only):# 0 layer 0 (only 1 layer can display YUV)# 1 layer 1 (default, only 1 layer can display YUV)# xres Display x resolution# yres Display y resolution# refresh Display vertical refresh rate, in Hz# pixclk Pixel clock frequency, in Hz# up Pixel clock up position, in ns (default 0)# down Pixel clock down position, in ns (default 15)# hsw Horizontal sync width# hss Horizontal sync start# hew Horizontal end width# vsw Vertical sync width# vss Vertical sync start# vew Vertical end width# vpol Vsync polarity:# 0 active low# 1 active high# hpol Hsync polarity:# 0 active low# 1 active high# epol Output enable polarity:# 0 active low# 1 active high# dpol Data polarity:# 0 straight polarity# 1 inverse polarity# cpol Clock polarity:# 0 straight polarity# 1 inverse polarity# LVDS settings (i.MX53+ only):# When ldbmode is not 0, the following caveats apply:# If both DIs are used with LDB, they must have identical pixclk. No checking is done for this case, but it won't work. Other# parameters may be different (e.g. width and height), but not pixclk. If the LDB is active and ldbclksel is zero, DPLLC4 will# be reprogrammed, extclk and hspclk are ignored. Behavior when ldbmode is configured such that one LDB channel is connected to# two DIs is undefined. If ldbmode is used on both DIs, one of the ldbmodes must be 1 and the other must be 2. If ldbclksel is# non-zero, the LDB is configured, but the DPLLC is not. This is used in cases where DPLLC is configured elsewhere, e.g. in# startup. ldbclksel=3 selects DPLLC3, 4 selects DPLLC4.# ldbmode LVDS display bridge output:# 0 disable (default)# 1 connect this DI to LVDS0# 2 connect this DI to LVDS1# 3 both# ldbmap LVDS display bridge channel bit mapping:# 0 SPWG (default)# 1 JEIDA (ldbwidth must be 1)# ldbwidth LVDS display bridge channel width:# 0 18 bits (default)# 1 24 bits# ldbclksel LVDS display bridge clock select (i.MX53 only):# 0 autoconfigure DPLLC4 (default)# 1 autoconfigure DPLLC4# 2 autoconfigure DPLLC4# 3 DPLLC3# 4 DPLLC4# The vidbase and vidsize entries are optional and should only be used in cases where contiguous memory for displayable and / or GPU# capable surfaces need to be reserved. Both vidbase and vidsize need to be specified in these cases. Specifying only one of them will# result in the driver not using the reserved memory. Note that when used, a matching reserved memory entry needs to be specified in the# startup options of the board's build file. When vidbase and vidsize are not specified, surfaces will be allocated when required, and# memory will not be reserved in advance for them. This is the default behaviour.# vidbase Physical base address of reserved memory for surfaces.# vidsize Size of reserved memory for surfaces.# At the end of any line that contains display options, all configuration settings on the line are applied to the current GF display.
Конфигурационный файл драйвера devg-imx6x.so позволяет задавать следующие параметры:
Параметры детектирования устройства:
Параметры определения режима вывода информации:
Параметры интерфейса LVDS (только для i.MX53+):
Freescale i.MX6 Quad development board (800x480 WVGA LCD module):
board=3,chip=63,ipu=0,di=0,type=1,ofmt=16,hspclk=264000000,xres=800,yres=480,refresh=60, pixclk=32264000,hsw=124,hss=60,hew=32,vsw=2,vss=33,vew=10,vpol=1,epol=1,dpol=0,cpol=0,hpol=1,yuv=1
Freescale i.MX6 Quad - Dolomant ONIKS08 (800x600 AUO 8.4 Inch Color TFT-LCD module "G084SN05 V9"):
board=3,chip=63,ipu=0,di=0,type=2,ofmt=24,hspclk=264000000,xres=800,yres=600,refresh=60, pixclk=39800000,hsw=128,hss=128,hew=1,vsw=14,vss=14,vew=1,vpol=1,epol=1,dpol=0,cpol=0,hpol=1,yuv=1,ldbmode=1,ldbmap=0,ldbwidth=1
Freescale i.MX6 Quad - TMR-Smartphone (720x1280 SSD2828 LCD):
board=3,chip=63,ipu=0,di=0,type=2,ofmt=24,hspclk=264000000,xres=720,yres=1280,refresh=60, pixclk=56320000,hsw=128,hss=128,hew=1,vsw=14,vss=14,vew=1,vpol=1,epol=1,dpol=0,cpol=0,hpol=1,yuv=1,up=-1,down=-1,ldbmode=1,ldbmap=0,ldbwidth=1,re-init=1
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